1. Field of the Invention
The present invention relates to a semiconductor device using a lead frame and a method of manufacturing the same.
2. Description of the Related Art
A portable electronic device has been downsized in recent years, and a semiconductor package to be used therein has accordingly been required to be downsized and thinned while securing a mounting strength. Employing a surface mount package has been known as a measure for downsizing the semiconductor package, in which an external terminal protrudes in parallel to a substrate mounting surface. Examples of this package type include a small outline non-lead package (SON) and a quad flat non-lead package (QFN). Those packages have a feature in that an external electrode for mounting the package on a substrate is smaller than that of a dual inline package (DIP) or a small outline package (SOP) that has been used in the related art, and hence a solder fillet is hardly formed after the package is mounted on the substrate, and it is difficult to obtain a sufficient mounting strength. Note that, those packages are often manufactured with use of a lead frame produced by using a stamping mold or processing of etching. As a material of the lead frame, a 194 alloy or a copper alloy is used in general.
In manufacturing of the semiconductor device using the lead frame, a semiconductor chip is mounted on the lead frame, and the semiconductor chip and the lead frame are electrically connected to each other via wires. The resultant structure is then subjected to resin encapsulation processing and burr processing, and exterior plating processing is carried out on the copper surface. After the exterior plating processing, the semiconductor device is cut off from the lead frame so as to have a predetermined size. As described above, the semiconductor device is cut off from the lead frame after the exterior plating processing, and hence no exterior plated film is formed on the cut surface of the external electrode. Accordingly there is a problem in that the solder wettability is poor when the semiconductor device is mounted on the substrate. In view of this, in order to improve the mounting strength of the semiconductor package produced under such conditions, it is proposed that the shape of a lead distal end portion be changed in plan view or cross-sectional view so that the solder wettability after the semiconductor device is mounted on the substrate is improved and a solder fillet is thus easily formed, to thereby increase the mounting strength (for example, see Japanese Patent Application Laid-open Nos. 2006-19465 and Hei 7-45769).
However, along with the progress in downsizing and thinning of a semiconductor device, it is required to further improve the substrate mounting strength of the semiconductor device.